Academic Hardware Products (myDAQ, myRIO)

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myRIO ADC latency and FPGA clock speed

Hello,

 

I have a project that is currently working with a cRIO. I am evaluating whether I can switch over to a little myRIO-1900 board since they are available now and cRIOs have a long lead time. I also like the smaller size and native I2C/SPI support and don't really need all the cRIO features.

 

One question I have is what is the input latency of the myRIO-1900 ADC? When I was getting my project working on the cRIO I initially used an ADC module that had a delta-sigma ADC which introduced about 800us of latency into the control loop I was running. I eventually switched to an SAR type module and the problem went away. Which type is used in the myRIO-1900?

 

Another concern I have is whether the myRIO-1900 supports 200Mhz FPGA derived clocks since I am using a SCTL at that speed to generate a fast PWM output in my cRIO application. Can the myRIO-1900 do that? I guess what I really need to know is the duty cycle resolution of the myRIO PWM output at 100kHz (max base frequency).

 

Thanks,

Mitcham

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