@Hooovahh wrote:
There are too many to list. Can you be more specific. What are you having an issue with? Is this related to an NI product like LabVIEW FPGA?
Fully agree.
Compile failures are typically due to running out of space (resources) or not meeting timing (clocks are too fast). The interact with each other. Too much resources (but not over the limit) could be realized as a timing failure.
Root cause is planning and design. Use of modeling and simulation followed by modular designs to try out parts first and get the bitness right for example. If a part is considered risky, figure out a way to confirm if the risk will ocurr.
The link in the first post is not for NI's FPGA products, so hard to know what the original poster wants to know.
