Additional counter inputs together with PXIe-6396, synchronization

[Stitz]

Hi

We are thinking to use the PXIe-6396 module for fast data aquisition of analoge signals and two quadrature encoders. Because of this, the counters in the PXIe-6396 are already used for the encoders, but we need 5 additional counter inputs. We were then thinking to add the PXIe-6614 counter module, but are not sure about the synchronization of the two cards. Which is the most elegant way to synchronize the analoge inputs, the counter inputs on the PXIe-6396 and the counter inputs on the PXIe-6614?

Also, is it preferrable to add a reconfigurable digital I/O module instead of the mentioned counter module? As far as we understand, we could use the FPGA on the module to implement counter inputs as well.

We have a source frequency of up to 25 MHz and would like to use the NI-DAQmx python library (FPGA programming would be done via Labview obviously).

Thank you for your advise!

Best regards,

Stephan

[Kevin_Price]

PXI systems have a backplane for sharing multiple clock and trigger signals and DAQmx can do most of the "dirty work" for you.  For example, if you want the Dev1 sample clock to sync up the sampling for Dev2 tasks, you would configure DAQmx Timing for those Dev2 tasks to use the signal "/Dev1/ai/SampleClock".  DAQmx will then manage any signal routing to get the clock out of Dev1, onto the PXI backplane, and into Dev2.

However, not all counter measurements are based on a regular sample clock.  Many of them tend to use "implicit" timing where the signal itself sets a potentially variable sample rate.  What are your non-encoder counters measuring?

-Kevin P

[Stitz]

Thanks for your fast feedback!

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@Kevin_Price wrote:

PXI systems have a backplane for sharing multiple clock and trigger signals and DAQmx can do most of the "dirty work" for you.  For example, if you want the Dev1 sample clock to sync up the sampling for Dev2 tasks, you would configure DAQmx Timing for those Dev2 tasks to use the signal "/Dev1/ai/SampleClock".  DAQmx will then manage any signal routing to get the clock out of Dev1, onto the PXI backplane, and into Dev2.

This was exactly where we were not sure, thanks for the explanation.

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@Kevin_Price wrote:

However, not all counter measurements are based on a regular sample clock.  Many of them tend to use "implicit" timing where the signal itself sets a potentially variable sample rate.  What are your non-encoder counters measuring?

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Our non-encoders will be used for edge-counting of signals. So each time we sample a new encoder and analoge value, we would also like to know how many pulses we have received since the last sample.

We are still wondering if a reconfigurable digital I/O module would be beneficial to a dedicated counter module?

Best regards,

Stephan

[Kevin_Price · Accepted solution]

Edge counting should sync up just fine with a simple shared sample clock.  A simple finite difference will give you the # pulses between consec samples.

The data acq for this app would be quite straightforward with a dedicated counter board like the 6614.  And counters provide quite a lot of flexibility for future uses.

Reconfigurable DIO would give you more "channels" of I/O and even more flexibility, but would also require LabVIEW FPGA-specific knowledge.

I'd personally opt for the counter board (or even 2 of them to provide more independent channels) over a reconfigurable DIO board unless the app demanded something the counter board(s) couldn't accomplish.

-Kevin P

[Stitz]

Thank you a lot for the feedback again, highly appreciated!

Best regards,

Stephan