Hardware. Frequency measurement/estimation (Analog)

[acanivell]

Hello

I need to measure the frequency of a single sinewave with these requirements:

- Sinewave frequency range: 1Khz - 100Khz
- Sinewave amplitude: 2V
- Sinewave offset: 8V
- ACCURACY: 0.1 Hz

Frequency estimation must be continuously done, refreshed in aprox. 1 second.

I thought about these hardware options:

- CRIO 9073 + 9435 input. Counting done in the CRIO FPGA.
- PXI  1033 + 6602 counter. Counting done by the 6602.

For both cases, my sinewave would have to be converted to TTL compliant pulses with an external Smidtch Trigger (as seen in http://digital.ni.com/public.nsf/allkb/771D82A44F27A0AF86256DD0007FB9A1?OpenDocument)

Questions:

- Is there a way to convert my sinewave in to TTL compliant pulses using the NI hardware I propose?
- Can i measure in analogue directly with this accuracy (Analog Period Measurement Express VI http://zone.ni.com/reference/en-XX/help/371599D-01/lvfpga/fpga_period_measurement/)? (by the way SCXI 1126 is not accurate enough)
- Do I necesarily need the FPGA module for this (I need min 1Mhz clock according to http://zone.ni.com/devzone/cda/tut/p/id/3619)

Any idea, suggestion or comment is very welcome !

[acanivell]

Just one piece of info I forgot to include:

- PXI solution: 6602 counter has got 75ppm stability on the oscillator

- CRIO solution: FPGA internal oscillator has got 200 ppm; 35 ppm at 25 °C stability on the oscillator

Therefore, I am also concerned about this stability being added to my overall error budget;

If we use a 10Mhz clock of 75ppm stability, I get 0.75Hz error in frequency, which is already above my error budget !

Therefore ideas/recommendations how to deal with CRIO and PXI internal oscillator errors would also be valuable.

Cheers

[acanivell]

After doing some calculations, motivated by this thread:http://forums.ni.com/ni/board/message?board.id=40&message.id=7582#M7582

It seems that derived clocks inherit the relative clock stability, not the relative. Therefore:

Let us say that the oscillator is 75ppb stable, 10Mhz. Now we generate 10Khz out of it.

The oscillator drifts from to 10,000,000.7500 to 9,999,999.2500 (according to the 75ppb=>0.75Hz drift). If we count 1000 cycles of this oscillator, we should have 10Khz, but according to these drifts, we will have a drifted 10Khz:

10000.00075 to 999.99925 Hz

Which corresponds to 0.00075 Hz drift, which is the oscillator drift divided by 1000 (0.75Hz / 1000).

So any clock derived by the oscillator will have stability:

Stability = CLOCK *XX [Hz]

Where XX is the proportional stability over a period of time, usually expressed as XX ppm per year.

This is just a partial answer to my first question, but as I read in the forums, I thought it would be nice to share with everybody.

[acanivell]

New calculations show that a 75ppb stable clock would be necessary, together with a more complex way to measure frequency, such as the divide down frequency method.

I summarize here the error calculations that intend to consider synchronization error together with oscillator stability error. I am not sure that they are 100% right, but I would appreciate some feedback (also in http://forums.ni.com/ni/board/message?board.id=40&message.id=7595&jump=true#M7595😞

Assuming that I use the divide down method for frequency estimation:

Clock freq         10,000,000.0000    Hz    

Signal freq         100,000 Hz

Frequency divider 10000 

After dividing down the signal's frequency with a 75ppb stability clock:

Divided down signal freq    10    Hz    (signal freq / freq divider)
Max divided down freq    10.00000075    Hz    (divided down signal + (stability * divided down signal))
Min divided down freq    9.99999925    Hz    (divided down signal - (stability * divided down signal))

Now if we coun this signal with its fluctuations, we get this oscillation in the counts:

Max count for signal    1000000    count    (max oscilat freq / min divided freq)
Min count for signal    999999    count    (min oscilat freq / max divided freq)

If we process these count numbers:

Max estimated freq    100000.1075    Hz    (max oscillat freq / min count * divider )
Min estimated freq    99999.9925    Hz    (min oscillat freq / max count * divider )

Therefore:

Absolute error    0.107500107    Hz    (maximum of the errors of both estimations)
Max measurement time    0.1    s    (frequency divider / signal frequency)

Which would be fine, slightly in the limit, but fine. For a 1Khz signal, same calculations would perform better, but require  10seconds measurement. For this reason the frequency divider value could be reduced without compromising the accuracy.

Which shows that a 6602 or a CRIO would not be good enoug, only a 6608 would be fine, if using the divide down method and a variable divide down value depending on the signal frequency.