How can I increase sampling rate? Active Noise Cancellation

[rhksgud92]

Hello

I am an undergraduate working on building Active noise cancellation code.

I could make good secondary path filter FPGA code (which could generate maximum 7k sampling rate).

However, my second FPGA code (for control filter) can generate maximum only 1.19 kHz. (The control filter FPGA code is attached.)

I need 2kHz sampling rate.

Since I am using memory storage method for matrix calculation, I think i can't use pipelining.

So I tried to increase sampling rate as much as i could by making calculation in parallel.

But as i increase the size of the function through parallelizing, compilation gets interrupted due to too much logics.

The file attached can generates 1.19kHz and uses 98.7% of slice LUTs.

What should i do to increase sampling rate?

[Daniel.Parrott]

It looks like it's just the number of times you're accessing the memory addresses that's slowing everything down. Is there anyway to consolidate the number of writes and reads to the memory blocks? 

Would it be possible for you to walk through the major parts of the VI you're working with? Just a high level overview of what each of those frames in the sequence structure does could help us find a better way of doing things.