x series, buffered edge count and duplicate count protection

[KimKimBo]

Dear All,

Just received a brand new X-series PCIe-6321!

Congratulations to NI for putting so many features in a nicely priced piece of hardware. 

I am a bit confused about buffered edge counting.

I intend to count asynchronous external edges coming to Ctr 0 using the AI sample clock, nothing fancy.

The counts can be cumulative but there is a possibility that, since the input is asynchronous, no edge could occur during a sampling period.

1) Do I need to use duplicate count protection?

2) If yes, is duplicate count protection still appropriate only for sources with frequencies < 1/4th of the max time base of the board (i.e., 100 MHz / 4)?

Thanks a lot for the answers.

P.S.: I am transitioning a legacy app from Traditional NI-DAQ (Text based programming, pure API calls) and I feel that NIDAQ-mx is over-engineered with little way to fine tune data acquisition. Am I the only old gizzard who thinks this way?

[stilly32]

1. X Series boards do not support duplicate count prevention since it is no longer needed - if there are no counts between sample clock edges then the board will simply return the same count.

Cheers, 

Andrew S

P.S.: You're probably not the only one that feels this way. Give DAQmx some time - 99.9% of the functionality is still there (FSK is the notable exception, but you can actually do that with X Series), its just been abstracted in some cases to make it easier to the average user to get into. While Traditional DAQ had a lower level feel (programming a two counter measurement by actaully programming two counters and routing the output of one to another) DAQmx just does a lot for you (just set the property to a two counter measurement and it will do everything else for you.) Feel free to post as needed and the forums can help you "translate" from Traditional DAQ to DAQmx - especially if you can give signal descriptions and end goals rather than TDAQ code. 

[KimKimBo]

Thanks for the answer. Everything I needed!

Best regards, 

[KimKimBo]

Two other questions regarding buffered edge counting in X series, just to clarify the documentations:

1) Is it possible to drive the counts from a PFIx input at frequencies up to 100 MHz? The spec sheet is not clear about this, there is mention of 25 MHz as the highest frequency for an external clock.

2) Do pulses need to be held high for at least 10 ns to be valid to the counters?

Thanks for answering these questions. 

[stilly32]

1) The counters are able to count at 100MHz, but the digital front end of the board is limited to 25MHz. With anything faster than 25MHz signal integrity starts to become an issue.

2) Same idea as question 1, the front end starts to become a limiting factor. I would stick with 20ns to be safe. 

Hope this helps, 

Andrew