Overview
These example projects implement Aurora 64B/66B streaming through the Nanopitch connector of Ultrascale FlexRIO instruments, such as the PXIe-7915 FlexRIO Coprocessor.
The projects were created from the NI 6591R/6592R Aurora Pattern Controller and Aurora Simple Streaming sample projects. The Socketed CLIP was replaced to support the Ultrascale FlexRIO instruments, while the host VIs for the eye scan support were copied from the PXIe-6593 Eye Scan example.
The Socketed CLIP included in the examples support a single x4 Aurora link on the Digital I/O connector of the PXIe-7915, with a line rate of 10.4167 Gb/s, therefore the Aurora configuration is fully compatible with the Aurora implementation used in the NI Streaming 5840 Host example available through VI Package Manager. Note that the Socketed CLIP included in these examples are different than the Socketed CLIP included in the Aurora 64b/66b Streaming Example for the PXIe-7915/Ultrascale FlexRIO. The Socketed CLIP in that project uses an Aurora core generated with a framing interface, while the Socketed CLIP in these projects uses an Aurora core generated with a streaming interface. When using the Aurora core, it is recommended to use the same interface (streaming or framing) on both endpoints. For example, the NI Streaming 5840 Host example uses an Aurora core with a streaming interface, using an Aurora core generated with a framing interface to communicate with the NI Streaming 5840 Host example may cause padding data to appear at the beginning of the data transmission and the last data beat to "stuck" in the Aurora endpoint if the framing control signals (tlast/tkeep) are not used.
The Aurora 64B66B Pattern Controller example project demonstrates how to generate, stream, and check data patterns on an FPGA target using the Aurora high-speed serial protocol with minimal interaction from the Host VI. Use the FPGA to generate and check sequences of data that are transmitted/received via Xilinx Aurora 64B/66B.
The Aurora 64B66B Simple Streaming example project demonstrates how to stream data between multiple FPGA targets and/or hosts using the Aurora high-speed serial protocol. Use DMA FIFOs to stream data between the Host and FPGA. Transmit/receive the stream data via Xilinx Aurora 64B/66B on the PXIe-7915.
Aurora 64B66B Pattern Controller
This project contains three top-level host VIs:
- Pattern Generator (Host).vi
- Pattern Checker (Host).vi
- Acquire Eye Scan (Host).vi
and one top-level FPGA VI:
- Pattern Controller (FPGA).vi
Pattern Generator (Host).vi allows you to generate and stream a pattern of your choice on the FPGA in real time. Pattern Generator (Host).vi also measures the effective data rate of the front end.
Pattern Checker (Host).vi allows you to read a data stream and monitor its integrity with respect to a reference sequence of your choice, which is run on the FPGA target.
Acquire Eye Scan (Host).vi provides debugging functionality by displaying a graphical representation of the link quality in a single lane.
Pattern Controller (FPGA).vi interfaces with the host VIs using controls/indicators and interfaces with the Socketed CLIP through AXI4-Stream and AXI4-Lite resources.
The PXIe-7915 IO Socket CLIP connects the Aurora 64B/66B protocol IP to the top-level IO signals, including the Multi-Gigabit Transceivers (MGTs).
- Aurora_64b66b_UltraScale.vhd is the top-level VHDL file for the IO Socket CLIP.
- Aurora_64b66b_UltraScale.xdc contains timing constraints for the IO Socket CLIP.
- aurora_64b66b.edf is a synthesized netlist containing the Xilinx Aurora 64B/66B protocol IP.
Running this example project
- This example includes a pre-compiled bitfile for the PXIe-7915 coprocessor. All host VIs are configured to use this pre-compiled bitfile so the example can be run without any compilation required.
- Connect the high-speed serial ports on the front panel of your PXIe-7915 targets. This example supports connecting between two different PXIe-7915 targets.
- Open Pattern Generator (Host).vi under the Aurora Pattern (UltraScale) (Host).lvlib library.
- Select an FPGA target from the TX FPGA Resource drop-down consistent with your cabling set-up before running the VI.
- Run the VI.
- Configure the sequence to your desired pattern.
- Open Pattern Checker (Host).vi under the Aurora Pattern (UltraScale) (Host).lvlib library.
- Select an FPGA target from the RX FPGA Resource drop-down consistent with your cabling set-up before running the VI.
- Run the VI.
- Change Sequence type to check.
- When the sequence type on the checker does not match the sequence type on the generator, the Mismatched cycle count will increase.
- Change the sequence type on the pattern generator to the same as on the pattern checker and the Mismatched cycle count will remain constant.
Aurora 64B66B Simple Streaming
This project contains three top-level host VIs:
- Continuous Stream Writer (Host).vi
- Finite Stream Reader (Host).vi
- Acquire Eye Scan (Host).vi
and one top-level FPGA VI:
- Streaming Controller (FPGA).vi
To facilitate streaming, the FPGA target contains two DMA FIFOs:
- Port 0 TX Input
- Port 0 RX Output
Continuous Stream Writer (Host).vi enables the input stream and continuously writes samples to the FPGA VI using the appropriate 'Input' DMA FIFO. Continuous Stream Writer (Host).vi also measures the effective data rate of the transfer stream.
Finite Stream Reader (Host).vi enables the output stream and reads a finite number of samples from the FPGA VI using the appropriate 'Output' DMA FIFO.
Acquire Eye Scan (Host).vi provides debugging functionality by displaying a graphical representation of the link quality in a single lane.
Streaming Controller (FPGA).vi interfaces with the host VIs using DMA FIFOs and interfaces with the Socketed CLIP through AXI4-Stream and AXI4-Lite resources.
The PXIe-7915 IO Socket CLIP connects the Aurora 64B/66B protocol IP to the top-level IO signals, including the Multi-Gigabit Transceivers (MGTs).
- Aurora_64b66b_UltraScale.vhd is the top-level VHDL file for the IO Socket CLIP.
- Aurora_64b66b_UltraScale.xdc contains timing constraints for the IO Socket CLIP.
- aurora_64b66b.edf is a synthesized netlist containing the Xilinx Aurora 64B/66B protocol IP.
Running this example project
- This example includes a pre-compiled bitfile for the PXIe-7915 coprocessor. All host VIs are configured to use this pre-compiled bitfile so the example can be run without any compilation required.
- Connect the high-speed serial ports on the front panel of your PXIe-7915 targets. This example supports connecting between two different PXIe-7915 targets.
- Open Finite Stream Reader (Host).vi under the Aurora Stream (UltraScale) (Host).lvlib library.
- Select an FPGA target from the RX FPGA Resource drop-down consistent with your cabling set-up before running the VI.
- Open Continuous Stream Writer (Host).vi under the Aurora Stream (UltraScale) (Host).lvlib library.
- Select an FPGA target from the TX FPGA Resource drop-down consistent with your cabling set-up before running the VI.
- If desired, customize the waveform generated using Wave Type and Frequency.
- Run Finite Stream Reader (Host).vi. The receiver stream is now waiting for data from the transmitter.
- Run Continuous Stream Writer (Host).vi. The Stream State indicator should read 'Continuous.'
- You can adjust the performance of your stream receiver using the Timeout and Samples Per Write controls. Increasing the timeout is primarily useful if you need more time to start the transmitter. Increasing the sample size allows you to take advantage of a system with more memory and CPU time.
- On Continuous Stream Writer (Host).vi, increasing Samples Per Write allows you to increase the TX Data Rate, depending on the speed of your CPU and the PCIe set-up.
- Click Stop Stream to stop the Continuous Stream Writer (Host).vi.
Hardware and Software Requirements
- NI PXIe-7915 FlexRIO Coprocessor
Running any of the examples in loopback configuration will require a Nano-Pitch wrapback assembly of some sort to connect the Tx and Rx Aurora streams. Otherwise a second PXIe-7915 or other module with a compatible Nano-Pitch interface is required such as a PXIe-5840, PXIe-5764, etc.
- LabVIEW 2018 or later
- LabVIEW FPGA Module 2018 or later
- FlexRIO 18.1 or later
Generating and Integrating Aurora IP into Your LabVIEW Project
For information about how to integrate Aurora IP into a LabVIEW project, refer to Knowledge Base article 6R6EOLM3.
The comments in the top-level VHDL file for the IO Socket CLIP (Aurora_64b66b_UltraScale.vhd) describe the Aurora 64B66B core configuration options used in this example, and also contains instructions on how to modify the CLIP to support a different Aurora 64B66B core configuration. Note that the Aurora core used by this example was created with Vivado 2019.1 (shipping with LabVIEW 2020). The Aurora core created with Vivado 2017.2 (shipping with LabVIEW 2018 and LabVIEW 2019) was causing pulse width timing violations during the bitfile generation, therefore it is recommended to use Vivado 2019.1 for generating the Aurora core support files (the aurora_64b66b.edf file).
Troubleshooting Signal Integrity Issues
An Eye Scan allows you to determine the quality of your link statistically. To run an Eye Scan on a receiver, follow these steps:
- Open Acquire Eye Scan (Host).vi under the Aurora Pattern (UltraScale) (Host).lvlib or the Aurora Stream (UltraScale) (Host).lvlib library.
- Select an FPGA Target from the FPGA Resource drop-down and select a channel to perform an Eye Scan on before running the VI.
- Run the VI.
- The graph will update to show you an Eye Diagram that represents the quality of the high-speed data link.
Common Issues
If you are trying to stream between two different devices and receive an error because the port is not ready but your cables are connected, run the VI on the other device and try again. There must be an active Aurora core on both sides of the connection for a high-speed serial link to be established.
If you see a single mismatch cycle the first time you run the Pattern Checker, that is most likely due to the implementation of the sequence checker on the FPGA. Because the sequence checker is self-seeding, the first sample taken after the FPGA resets may generate one mismatch while the sequence checker is re-seeded.
