sb-RIO9651 socketed CLIP

[Nathan_R]

HI Samuel-L,

This discussion is several years old. Is there an issue you need help with? It might be easier to create a new topic.

Thanks,

[Samuel-L]

Hello Nathan：
I refer to https://www.ni.com/pdf/manuals/375463b.pdf and https://www.ni.com/pdf/manuals/375536c.pdf these two specifications, These documents give me an idea that I want to expand a CAN port outside the RMC interface. Now, I have a problem, I can't generate CILP file，Here's how I do it，First of all, SBRIO 9607 is connected to a PC through a network cable. Set the IP of the PC to 192.168.0.1 and turn on NI Max to show that it has been connected, as shown in Figure 1.
Then, as shown in Figure 2, the Sbrio CLIP is generated with the name CAN, the peripherals CAN1 selected, and the rest the default Settings.
Figure 2
As shown in Figure 3, component-level IP is generated and syntax errors occur while checking the syntax.
Syntax error occurred while checking syntax while generating component-level IP. Can you help me? My email is shengyong47@163.com

Thanks，

Samuel-L

[Nathan_R]

Hi Samuel,

The problem is what you are doing in figure 3. That step is not needed for socketed clips created using the generator. To use the socketed clip you created in figure 2. Just right click on the RMC socket under the FPGA target in the project and select Properties. Then select the clip's xml file. It will just work from there. 

Thanks,

[Samuel-L]

Hi Nathan，

Thank you for your help. Now I have operated it again according to your idea, but the definition interface I want has not been generated. just like figure 4.Why does this problem occur?

I am very confused about how to use NI Sbrio 9607 and NI 9694 to create a new peripheral CAN interface and look forward to hearing from you.

Yours sincerely,

Samuel

[Nathan_R]

The CAN port is not accessible through the FPGA. It is a CAN port on the CPU in RT. The FPGA pins are just used to expose it. Once you have the socketed clip in the project you will need to compile a bit file for the FPGA. This can be done even with a blank VI. You then need to upload this bitfile to the sbRIO target to  run on boot. Reboot the sbRIO and the CAN port will now show up in MAX like the built in serial / CAN ports.

Thanks,

[Samuel-L]

Hi Nathan，

Thank you for your letter.Now I CAN generate cilp file, but I do not understand the meaning of adding RX,TX and RS to the Sbrio cilp generator. For example, if I add RX as DIO_0,TX as DIO_1,RS as DIO_2, then I cannot select interfaces such as DIO_0,1,2 when selecting LabVIEW interface. So if I define RX, TX, RS as DIO_0, what is the meaning of 1,2? This is very confusing to me.Or does NI have an example of 9607 and 9694 developing a second CAN port. Thank you for your next letter.

Sincerely

Samuel

[Nathan_R]

The DIO you select for the three CAN signals, (TX,RX,RS) is reserved for the CPU CAN port you are creating. You cannot use them as LVFPGA signals later because they are already being used by the CAN port. Note: you still need CAN transceiver HW connected to the 9694 to get a true CAN port. See page 28 of the NI sbRIO-9607/9627 RIO Mezzanine Card Design Guide for an example of the external circuitry.

Thanks,

[Samuel-L]

Hi Nathan，

Your letter has solved a lot of my confusion. I feel embarrassed to ask you some small questions, but I still want to ask this CAN transceiver to connect to 9694 to get a true CAN port. Then connect the three pins (TX,RX,RS) of the circuit diagram on Page28 to the ones I defined (tx-dio_1, rx-dio_2, rs-dio_3) on 9694. I plug in the pins I defined on 9694, use cilp generator or not? Or write FPGA port DIO_1,DIO_2,DIO_3 directly in LabVIEW, CAN receive the signal sent by CAN transceiver. After receiving the signal, CAN I directly use NI's CAN embedded driver control to convert?

Thanks，

Your sincerely

Samuel