IF-RIO ADC and DAC sample Rate

[thill]

Hi,

This may be more of a generic LV FPGA question, but I wanted to verify that if I am using an analog input in a SCTL, then I will get (1/clock rate) for the resolution between samples.  Is this correct and does it work the same way on the output?  I am very familiar with LV FPGA, but I have never used any of the IO on any card.  (I have used R-Series cards in the past with DMA and will be using the IF-RIO for this project).  

The reason I ask is because the data sheet for the 5640R states that there is an inherent decimation of M=4 on the ADC and then a interpolation of L=4 on the DAC.  I am trying to achieve a 8.33 ns resolution between samples (120 MHz clock) for this project and I don't know if this is going to throw a big issue into the problem.

Thanks

[JerryAL]

Hi

On the IF-RIO, you must use the AI and AO in a SCTL.  This guarantees that data is passed correctly from and to the ADCs and DACs.

You will have an issues in achieving a 8.333 ns period clock on the IF-RIO.  The Basic clocks for the ADC, DAC and RTSI clock are divided down from 200 MHz by values of 1,2,4,8, and 16. Ie, your RTSI clock can be 200 MHz, 100 MHz, 50

MHz, 25 MHz and 12.5 MHz.  These are basically the same clocks available to the ADCs and DACs.

Then you have the issue of the decimation and interpolation on the ADCs and DACs.  The maximum IQ rate is 25 MSps for the ADC and 50 MSps for the DACs, so you will not be able to get a 120 MHz IQ rate for the acquired data.

What is critical about this IQ rate?

Jerry

[thill]

The 120 MHz isn't very important.  I keep thinking in terms of the R-Series card that I've been working with.  We should be able to work around using the IQ rates you have listed.