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[arafat]

Hi,

I am new to labview, i compile the am demodulation in pci 5640 example but it can't.tell me some solutions n suggestions

[Vinay_Kumar]

Hi Arafat,

Please do mention the details of the problem, with error screen-shots. The attached AM demodulator works fine on my machine. Let me know if it does not work.

Note, this example does the demodulation on the PC. The FPGA is used only to acquire the signals and sends it to the PC.

--Vinay

National Instruments R&D

[arafat]

Hello Mr.vinay, this is from arafat, i run this program but it provides some error in fpga vi ( FIFO Governing library is an incomplete version) and i also have a doubt on how to give the input to this program and what is mean by the error visa resource is not available(how to access visa resourse).plese reply me sir. thanking you sheik arafat

[Vinay_Kumar]

Hi Arafat,

1.  Which version of LabVIEW are you using? LabVIEW 8.5 or LabVIEW 8.5.1.You can find this out by launching LabVIEW and then select help>> about labview.

The project which i have sent you was written using 8.5.1. If you are opening the VI in 8.5 then, the solution is to replace the existing FIFO Read, FIFO Write and FIFO Clear methods in the FPGA VI by deleting them and placing new instances using the Functions Palette. You will have to recompile.

http://ae.natinst.com/operations/ae/public.nsf/web/searchinternal/cc6493f9eb598cc78625744d005eef5d?O...

2.  The project expects an external input (connected to Analog Input Channel 0). So you will have to use an RF signal generator or another IF-RIO. If you are using a second IF-RIO then the following link might be of help. http://decibel.ni.com/content/docs/DOC-1710.

If you want to use an NI-RFSG then you can use the example which ships with the RFSG drivers.

3.  Are you still getting visa resource is not available? Are you using a valid resource name when running the project?

You can find the resource name of the device from drop down control "resource name" or from MAX.

You can find more details on VISA (if you are interested) here http://cnx.org/content/m12288/latest/

Can you please send me the screen shot of the error? Also please do specify the LabVIEW version you are using.

Hope this helps.

--Vinay

[arafat · Accepted solution]

hi vinay, I changed that module according to 8.5 now fpga is running and i connect the am signal (21.4 MHz)in the AI channel 0 but error 61059 occur error message is Error -61059 occurred at Read/Write Control : Config.ADC 0 Microport Address in ni5640R AM Demod.lvlib:ni5640R ADC address_port_write.vi->ni5640R AM Demod.lvlib:ni5640R ADC read_write.vi->ni5640R AM Demod.lvlib:ni5640R ADC read_write (multi-byte).vi->ni5640R AM Demod.lvlib:ni5640R ADC write_register.vi->ni5640R AM Demod.lvlib:ni5640R ADC 01 - Chip IO Access.vi->ni5640R AM Demod.lvlib:ni5640R ADC Global.vi->ni5640R AM Demod.lvlib:ni5640R ADC Default.vi->ni5640R AM Demod (HOST).vi please give the solution sir. thanking you I.sheik arafat

[arafat]

hi Mr.vinay, This is arafat I compile the fpga by ur guidence now i connected the AM signal with 21.4 MHz gave as the input in AI channel 0 but i run the program it gives on the error Error -61059 occurred at Read/Write Control : Config.ADC 0 Microport Address in ni5640R AM Demod.lvlib:ni5640R ADC address_port_write.vi->ni5640R AM Demod.lvlib:ni5640R ADC read_write.vi->ni5640R AM Demod.lvlib:ni5640R ADC read_write (multi-byte).vi->ni5640R AM Demod.lvlib:ni5640R ADC write_register.vi->ni5640R AM Demod.lvlib:ni5640R ADC 01 - Chip IO Access.vi->ni5640R AM Demod.lvlib:ni5640R ADC Global.vi->ni5640R AM Demod.lvlib:ni5640R ADC Default.vi->ni5640R AM Demod (HOST).vi give me solution for that

[Vinay_Kumar]

Hi Arafat,

In the Host VI, please do the following.

1. Right click on the FPGA open session.

2. Goto select VI, choose the FPGA VI that you have recompiled.

3. Right click again on the FPGA open session.

4. Goto select Bind to Typedef and choose the  ni5640R FPGA VI Reference.ctl which is located in the project directory, NI-5640R VIs folder. Make sure you are using the correct folder.

The Host might show error after this. To solve this, please do the following,

1. Open the FPGA driver VIs, (the VIs in Green, labeled NI-5640R).

2. On the front panel, right click on "HW Exec Ref" inside HW Exec Ref In control and select Open Typedef. A custom control (looks like a VI) will open. Simply Save this and close.

3. Save and Close the driver VIs. If you see a read dot or a wire broken, simply open the VI and same them again.

This should solve the issue.

This is a work-around for this problem and is being fixed in the new version of the driver.

 If you have issues related to this problem, please do send me the project with the necessary files.

--Vinay