Importing IP issue (HDL port not recognised)

[Phy_comm]

I am trying to import an IP in to my FPGA based design. I tried with some codes which worked perfectly fine.

But in some case like when synthesising atan2 or awgn sample codes from VIVADO HLS by Xilinx it's unable to work by either of the way:

a) Directly importing top .vhd file in External HDL IP form for EIP.

b) Importing exported RTL IP in IP-XACT format from VIVADO HLS.

In both the case it fails to recognise top .vhd file.

And HDL port names are not recognised too.

When I press Parse and Verify error is shown as given the attached figure.

Please assist in configuring the IP.