Use rare FPGA Build without Sample FPGA Build

[EtuelDue]

Hello,

I hope i can formulate my question in the right way. I want to test some FPGA routine and don't always want to compilate the hole  streaming project (e.g. the build with the register bus etc.). Is it possible to only build a simple FPGA bitfile (simple while loop, some fifos, my code) and test it on the USRP RIO device or do I have to use the basic FPGA Streaming Xcvr build as basis? This would really shorten the compilation time to test new code.

I hope my question is understandable.

Regards

Etuel

[brooksprumo · Accepted solution]

Yes, you can start from a blank FPGA VI and develop FPGA code similar to other LabVIEW FPGA targets. There are a few things to point out:

• You will not be able to use the Sample Project host VIs if you do this. If you do not have the FPGA code from the Sample Project, the host VIs will not have the correct FPGA logic to communicate with.
• I recommend not putting any code in the Data Clock domain. The Data Clock requires the USRP RIO IDLs to configure this clock domain. To do that correctly, you need the "Required" section of the FPGA block diagram. It's easier to just avoid all of this. To use clocks faster than the 40 MHz clock, derive a new clock from the 40 MHz clock.

Good luck!

[EtuelDue]

Hello brooksprumo,

thank you for your answer. Just to clarify the points you made: Can I use then this uploaded structure of my screenshots to test some FPGA code? The screenshot FPGA_Loop.png  shows that I just want to send data to the FPGA via FIFO and get the results back. In PC.png I build together the FPGA chain to upload the data and get the results back. Can this be done? I just don't want to damage the device in some way.

Thank you again.

Regards

Etuel

[National_Burritos · Accepted solution]

Hi Etuel,

That should definitely work; you won't damage the device, that is the point of software-configurable FPGAs! When actually connecting to I/O, I would recommend integrating with the Sample Streaming Project since it takes care of a lot of the hardware configuration, clocking, etc.

As a recommendation - are you using a host testbench before your FPGA test bench? It is always best practice to create a testbench on the host for FPGA algorithmic code. You can use the Run FPGA Simulation node to bring in your CDL code to a host testbench. This was you can test code before running a compile!

Cheers,

[EtuelDue]

Hello Rahul,

thank you for your answer. I am using a FPGA testbench, but at some point I wanted to try the algorithms on the FPGA and compiling the Sample Streaming Project together with my additions takes about 2 hours. But thanks nevertheless for the hint!

Regards,

Etuel