VHDL code integration?

[beck.278]

Hi everyone,

We've been developing OFDM and SOQPSK-TG transmitter and receiver hardware in FPGA using the design suite. Previously we were using LabVIEW FPGA. 

My question is, how do you import pre-written VHDL code to be compiled in the design suite? I cannot seem to figure out how to do this, which was possible with LabVIEW FPGA software. Which type of FPGA-targeted VI would you start with?

Thanks!

-Brian

[[dk]]

I would definitely recommend trying to repair/reinstall VeriStand since you have the code working flawlessly on another set up (could be a corrupt install).

I not familiar with any cRIO hard drive test off the top of my head, but let me look into that and see if we can come up with anything.

Also, for best practices in VeriStand, the closest thing I can recommend is the Getting Started materials but this is probably not helpful to you. The next thing would be the actual training but I understand that may not be doable as well. Just from your description of your architecture, I do not see anything inherently wrong but I would have to take a look at the project itself to know for sure.

[beck.278]

I'm having a hard time comprehending that response.  In fact I think you may have posted to the wrong topic...I don't even know what VeriStand is.

[[dk]]

I am so sorry! I replied to the wrong forum! Completely my fault!

[beck.278]

Wow for a second there I thought I was crazy! No worries .  Hopefully another engineer will get back to me on this one.

[beck.278]

Has no one else experienced this question?

[[dk]]

So I was able to check with a few colleagues and confirm that LabVIEW Communications does not currently support VHDL integration as does LabVIEW FPGA.

[T-REX$ · Accepted solution]

Actually, while it's not well supported, it's also not impossible...

The general process is to create an IP-XACT file, and use that. There should be an example of what this looks like in the 579x or USRP sample projects.

[adamarnesen]

In LabVIEW Comms we use the  .eip extension to pull external VHDL in using IP-XACT as a backing description of that IP. You can find them to your project under resources on the FPGA target.

The .eip file is an IP-XACT file and you should be able to follow the pattern of those files in one contained in the USRP sampleprojects to get your VHDL working. 

[Nick-C]

All,

We have a created a KnowledgeBase article which describes integrating 3rd party FPGA IP in LabVIEW Communication 1.0 in more depth.