Does anybody know what it takes to use the Microblaze MCS IP from a LabVIEW FPGA project that targets the PXIe-6592 High-Speed Serial Board?
I am using Vivado 2014.2, I have been able to create a simple core, import it as a CLIP node, but when I am doing this for the Microblaze MCS I am running in to some confusion with regards to the bmm file, how to properly overlay the elf file and how to set up my constraints. (I know how to overlay an elf file from Vivado, but I have to generate a bitstream first, but I don't know how to generate a bitstream unless I set up my constraints properly, but since I am targeting just the FPGA and not a Xilinx starter board, I do not know how to set up my constraints properly, and finally if I create a bitstream from Vivado, that won't help me much because I dont want to import a bitstream via a CLIP node.)
I have done this before for older targets that used the ISE (Virtex-5) environment, but have not figured this out yet for Vivado.
Any advice/tips? I am currently reading as much as I can on constraints and BRAM/BMM.
Thanks in advance
