Hello
I have to implement an application to 2 different things (confidential) on a USB-7856R, the 1st action is already implemented on a program that uses 80 percent capacity of the FPGA and the 2nd action is 50 percent of the capacity, which recently was developed.
To live with both processes we have being downloading the FPGA program sequentially, for prototypes this is OK, my concern is about write cycles limitation of the FPGA, I cannot find documentation about how many write cycles the device can handle, does any one knows?
From my years of college I remember write cycles are not infinite, and by looking up on the web I get a 1,000,000 million cycles as the most common answer, if that is true, in production this will only last 1 year, before I need a new FPGA
Iny ideas of how to workaround this will be very helpful.
