I am currently writing FPGA code (consider me a developing novice when it comes to programming), and have come across a few questions. Before I pose the questions I'll shed light on the needs of the FPGA vi I am writing:
data acquisition I/O of:
16 thermcouple inputs (4 tc modules 9211s)
16 4-20mA inputs (2 9203s)
1 Digital Input (magnetic RPM pick-up via the 9401 module.... is there another way to bring this pick-up in?)
9 Analog Outputs (16 AO module) .... with 7 of thes AO channels I'd like to have PID capabilities for these.
Possibly using a 9237 to bring in my load cell/strain gauge input (I was toying with the notion of using a 4-20mA signal transmitter to amplify the load cell signal so as avoiding having to run a higher speed loop with the 9237 module).
I am looking to bring in the analog inputs as efficiently as possible, and thus came up with the question of whether or not I could have three separate while loops (loop 1 containing the thermocouple modules, loop 2 containing the 4-20mA modules, and loop 3 containing the digital I/O module) feeding into one main DMA FIFO. I had come across a bit of info that this may screw up the order of the DAQ info coming across to the RT, but I still wasn't sure on this.... any input on how this would play out? I could possibly do 1 other thing with both the TC and 4-20 mA nodes ( to combine the TC inputs with the 4-20 mA inputs in the same I/O FPGA Node, wire all of these inputs into a build array, and then wire the array into the DMA FIFO .... though would this be too many inputs per one node? 32 inputs. And what of sampling the 4-20mA inputs 10 to 15 times per second, and only sampling the TC inputs at 3 to 4 times per second, would this screw anything up?
I possibly could take all the TC channels and build them into a cluster via a bundle, and use Front Panel Comm to pass the data from the FPGA to the RT... or I could possibly just use an interrupt for the TCs, and a DMA FIFO for the 4-20mA.
Where I am pretty hazy at right now is in regards to how efficient data transfer techniques from FPGA to the RT really are.
Message Edited by jonathandkr on
03-01-2008 12:24 AM