I have an application where I need to synchonize the clock on a 5761 to an external 10Mhz clock , and then have the
250 Mhz digitization exactly synched tot he clock. Since the multi-sample clip run =s the FPGA at 125 mHz, the
PLL on the 5761 must be sythesizing the 125 Mhz, which is not commensurate with the 10 Mhz reference clock period. So eacht ime i start up to take data the PLL 125 Mhz is shifted in phase wrt toe 10Mhz reference signal.
I want to compile the multi-sample clip to run at either 120 Mhz clock or 130 Mhz clock, PLL locked to the 10 Mhz clock input of the 5761. How do I do this?
I can see how to generate 120 Mhz and 13Mhz derived clocks in the project, but the FPGA compiler will reject these and only compile when the FPGA clock is set to IOModule/Data Clock as the IOModule/AI Data resoruces cant use anything but IOModule/Data Clock.
