I am writing a data acquisition code for the 7962R with the 5752 Adapter Module using LabVIEW 2012. The basic idea is similar to the "Finite Acquisition Multiple Channels" example with additional features for larger data sets. The FPGA waits for a trigger on the PXI backpane; acquires a 16 channels at a user defined rate (~10 MHz) for a user defined number of points (> 10K); and saves them to the DRAM. Once this is completed, the DRAM then transfers the data to the host computer using a DMA FIFO. For small sets of data I can get this to work storing data in target scoped FIFOs. However, now that I have added DRAM, the code seems to work the first time the acquire button is pressed, then on subsequent acquires, returns the correct number of points all with a single value. I am currently using the DRAM as a FIFO, as this seemed the simplest implimentation. I understand there are alternatives, but am unsure if I made the correct choice. Also, if I understand correctly, the analog channels must be acquired using the IO clock on the 5752 card. Can I use this same clock for writing and reading data to and from the DRAM? Any suggestions as to why each channel has a fixed value after the first acquire would be greatly appreciated. Thanks.

LabVIEW

Adding DRAM storage to "Finite Acquisition Multiple Channels" on FPGA

jp82,

I see and I am sorry for the misunderstanding. I think the easiest way to implement the clear DRAM would be to have a state at the beginning of the state machine that cleared the DRAM. Once the Data Available both go to false, the OR will be FALSE and it will go to the "Waiting for Trigger" state just you it would before. I created a new state called "Clear DRAM". I think I am passing everything through correctly to your shift registers but you might double check this. It would be helpful in future to create typedef for your state enum so you do not have to re-add in all places reference in your code after you add a case.