09-24-2019 07:09 AM - edited 09-24-2019 07:10 AM
AFAIK, the RT "Open FPGA Reference" Refers to the FPGA portion of your project to query the VI status, where the FPGA target claims the source has changed (because the RT has re-compiled part of it).
You said you have it linked to a VI, not a bitfile? I prefer bitfiles. Less flexible but don't suffer from this kind of problem.
09-25-2019 10:07 AM
Once I switched to referring to the bitfile, the problem went away. I think that makes sense - it no longer thinks anything is different.