Block Memory and Read Latency outside SCTL

[Gryffin]

I have a simple question about LabVIEW FPGA which I believe is causing me trouble:

If I am reading a block memory outside of a SCTL (in a normal while loop) and the block memory has 2 cycles of read latency, will the block memory provide a proper value in a given iteration without any pipelining or other considerations?

Thank you

[Terry_ALE]

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@Gryffin wrote:

I have a simple question about LabVIEW FPGA which I believe is causing me trouble:

If I am reading a block memory outside of a SCTL (in a normal while loop) and the block memory has 2 cycles of read latency, will the block memory provide a proper value in a given iteration without any pipelining or other considerations?

Thank you

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I have only used it in a SCTL.  I think this could be tried out in a simple test VI.

[Intaris · Accepted solution]

I've only ever used SCTLs, but I think normal while loops handle all of the latencies in the background, so yes I think it should return a valid value each time. But this needs to be tested in a VI.