Broken Wire at compiling FPGA and Host Vi

[marccoular]

I created a new embedded project file. The Host and FPGA Vis are included to this project and the Host Vi is set as TopLevel. When I open the Vis there is no broken wire.
But when i want to compile them and download them to the FPGA i get an error message about broken wires. After that there are broken wire in the Host Vi, not on in he FPGA-Vi. There is a function to get some values from Teststand. This doesn't work and also the connection to the sequece context input is broken. That lead to other broken wire in the Vi.
There is Teststand 3.1 and LV 7.1 installed.

[Dippi]

Hi marccoular,

perhaps you could give me a little more specific information.

And perhaps it is possible to attach your project here, if it is not too big.

Regards
Dippi

[marccoular]

OK we use the PXI7831R FPGA module. The version of LabVIEW FPGA is 1.1.
I attached the Host an FPGA VIs. Also the project file is attached.

[Dippi]

Hi marccoular,

I solved your problem here.
The fault was, that you insert both VIs (FPGA and Host) to the project.
I changed this. Only the FPGA VI should be part of the project -> the host VI should run on the Windows computer.

Best Regards
Dippi

[marccoular]

Hmm... Ok but i just thought that there is a need of inserting both FPGA and Host to the project file and setting host as toplevel.

[Christian_L]

In LabVIEW 7.x, the project only contains FPGA specific VIs. The Top Level VI is the one that will be compiled and will be downloaded to the FPGA from the host VI (which is not part of the project).

Starting with LabVIEW 8, the new LabVIEW project contains all targets (Windows, RT, FPGA, PDA, etc.) and you manage all of your application VIs as well as application distributions, etc. in the project.