CompactRIO Digital lines max speed

[crossrulz]

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@UMASO wrote:

By the way, in your configuration with 9402, DI is working at 40MHz, while its specification is 16MHz with 4-channel, and 20MHz with 2-channel, as described in 9402 specification below.  

How many channels are you using with the current configuration?  4 channels?  

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2 channels.  Maybe I'm just getting lucky.  It is working on 3 setups right now.

[Jacobson-ni]

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@UMASO wrote:

Thanks for correcting my post above.  Crrect statement should be "cRIO DIO can be placed inside SCTL with 40MHz onboard clock, and cannot be placed any other clocks such as derived clocks."  

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I believe all DIO in a cRIO can be placed inside of a SCTL as long as the rate is a multiple of 40MHz. If you try to compile a VI with a 9402 in a different time domain it will produce an error during intermediate file generation that will tell you this.

As for crossrulz running at a higher rate than what the specifications claim, I know that for DIO in sbRIOs you can put the DIO in a SCTL running at any rate but that doesn't mean the output will look very clean so it might be something like that. It might not actually be meeting all of the written specifications when used at a higher rate but that might still be good enough for whatever crossrulz is connected to.

[OmarKhaledAli]

Thanks for your answer, I think I will try to go with using the external clock at first, so I am thinking to use the CLIP and add the 10 MHz CLK in my system as an external clock in the FPGA and to use it as the clock in the SCTL, I can't find a clear tutorial to add external clock to the FPGA and use it in the LabVIEW FPGA code, or should I write my code as a VHDL and include this code in the CLIP. if you can support me with a clear tutorial or so that would be great.

[UMASO]

Author started a new thread below.  Let me paste the URL below for a reference.  

https://forums.ni.com/t5/LabVIEW/SbRIO-9651-external-clock/m-p/4286737