Compilation Error in LabVIEW FPGA -Unspecified I/O Standard ​

[johnsnow34]

Hello everyone,

I am using Labview 2018 fpga modul. I am trying to compile a VI file through Vivado 2017.2

But there is a error like this:

ERROR: [DRC NSTD-1] Unspecified I/O Standard: 18 out of 192 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. 

According to the error message, I should specify all I/O standards. In the picture is the i/o name and the vi file is in the attachment. Some solutions on the Internet say that the constraint file should be edited with HDL. But how to solve this problem in Labview fpga?

Any reply will be appreciated!

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[DStavilaNI · Accepted solution]

Hey John,

              I think that you need to generate first a CLIP for your sbRIO and the SOM interface, then add it to your sbRIO target in the project. I think that it is rather well explained in the presentation attached to this forum thread:  sbRIO-9651 SOM IO Interface and CLIP Generator.pptx

 

I hope this helps.

Sincerely yours,

Denis

[johnsnow34]

Hi Denis,

thanks for the reply. The problem has been solved. Yeah, as you said, I generate a new CLIP and now everything works fine.