Conversion from U32 to FXP on host side after FIFO DMA transfer

[raphschru]

@Intaris, I see the interest of the "Reinterpret Number" FPGA Node, but in the present case you have to change sizes anyway (24bit <-> 32bit) to comply with the chosen FIFO type. But I agree that FXP representation of constants / controls / node outputs are not visible at all. LabVIEW FPGA could be improved if we had the possibility to make it visible on the block diagram directly.

[Intaris]

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@raphschru wrote:

@Intaris, I see the interest of the "Reinterpret Number" FPGA Node, but in the present case you have to change sizes anyway (24bit <-> 32bit) to comply with the chosen FIFO type. But I agree that FXP representation of constants / controls / node outputs are not visible at all. LabVIEW FPGA could be improved if we had the possibility to make it visible on the block diagram directly.

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Out of curiosity, where do you see the conversion from 24-bit to 32 and back? I've re-read this thread and the other you've linked to and see no mention of changes in bit width. Is this just familiarity with the device?

[raphschru]

Because his FXP value comes from an NI 9222 analog input (Mod6/AI0), which is a FXP <±,24,5> in "Calibrated" mode, and he wants to send it via a U32 DMA FIFO. Why U32 FIFO ? Because he is also sending SENT data which is also U32, so this configuration is the most logical in my opinion.

[Tom_wolf]

Hi Raphael,

First test has shown this solution works 😊

Thank You for support.

P.s I promise not to multiply threads if further doubts around this matter arise.