Customizing single port SPI example for TI ADS1675

[Mariano76]

Hello,

i've designed and built an ADS1675 based board.

I pulled out following ADS1675 pins available to a 50pin connector:

1. FPGA CLK
2. DRDY
3. /DRDY
4. DOUT
5. /DOUT
6. SCLK
7. /SCLK
8. CLK_SEL
9. LVDS
10. LL_CFG
11. /CS
12. FPATH
13. DR0
14. DR1
15. DR2
16. START

i've interfaced this pins with DIO connectors of sbRIO 9602 

Can you please tell me how to modify single port SPI example to read data through sbRIO9602 ? 

I'm trying also to make code at http://forums.ni.com/t5/LabVIEW/Help-with-Labview-code-for-reading-ADC-data-with-7811R-DAQ-board/td-... work, but without success...

Thanks and Regards.

MR

[FatBoyMonchi]

Hi Mariano,

I think the better way is to start with a new project, adding your sbRIO and the modules you're going to use (which DIO module do you want to use?).

After adding the whole hw stuff, copy the VIs in the same position and look what to modify inside the code to adapt it to your hw.

Let me know!

Bye

FBM

[Mariano76]

Hello,

i'm here after a while to check board HW and i can finally say that it's working  so now i have to interface it to sbRIO,

my board now is setted in a way that it delivers SCLK, DATA READY, and DATA OUT and with CS always tied low..

i have not so clear the concept of who plays the role of MASTER and who the SLAVE in the communication between RIO - ADC..

i'm trying to build a very simple FPGA VI to retrieve DATA OUT bits when DRDY goes HIGH but until now i still haven't found a working solution.

From timing characteristics when CMOS output and LOW SPEED are selected i cannot figure out if every single bit of DATA OUT is available on every rising edge of SCLK...

on page 8 of ADS1675 data sheet seems that DOUT and SCLK internal are not synchronous... 

Have you some VI  specifically developed for communication with NI FPGA - ADS1675?

I've done a main while loop inwhich in a 1st SCTL i look for DRDY going HIGH and after in a 2nd SCTL i look for rising edges of SCLK and on that i read DOUT pin to store 24 bits in an array...but just cannot read them... maybe there are some delays to consider or some rules to follow to build a basic SPI  communication FPGA VI just to check bits delivered out from ADC...

is there some good in details tutorial of some of SPI examples work?

Thanks in advance!

MR