DMA RT to FPGA guaranteed order?

[Intaris]

I have a question regarding the sending of data via FIFO to an FPGA card via DMA.  I would assume that if I have several locations in my RT code sending data via DMA FIFO that it is still guaranteed that any given DMA Transfer (let's say 12 data values) are delivered atomically.  That is to say that each DMA node data is sent as a contiguous block.

Take the following example.  I have two DMA FIFO nodes in parallel.  I don't know which is going to be executed first, and they will most of the time be vying for bandwidth.  Both nodes send over the SAME DMA FIFO.  Does the data arrive interleaved, or is each sent block guaranteed to be contiguous ont he receiving end.  Do I end up with

Data0 (Faster node)

Data1 (Faster node)

Data2 (Faster node)

Data3 (Faster node)

...

Data11 (Faster node)

Data0 (Slower node)

Data1 (Slower node)

..

Data11 (Slower node)

or do the individual items get interleaved.

I'm kind of assuming that they remain in a contiguous block which I'm also hoping for because I want to abuse the DMA FIFO as a built-in timing source for a specific functionality I require on my FPGA board.  I can then use the RT-FPGA DMA Buffer to queue up my commands and still have them execute in perfect determinism (Until the end of the data in my single DMA transfer of course).

Shane.

[GregFreeman]

Woah, new avatar. Confusing! 

I am going to preface this by saying that I am making assumptions, and in no way is this a definitive answer. In general, I have always had to do FPGA to RT streaming through a FIFO and not the other way around.

When writing to the FPGA from the RT, does the FIFO.write method accept an array of data as the input? I'm assuming it does. If so, I'd then make the assumption that the node is blocking (like most everything else in LabVIEW). in which case the data would all be queued up contiguously. Interleaving would imply that two parallel writes would have to know about each other, and the program would wait for both writes to execute so that it could interleave the data. That doesn't seem possible (or if it was, this would be an awful design decision because what if one of the writes never executed).

Of course, this is all assuming that I am understanding what you are asking.

You're probably safe assuming the blocks are contigous. Can you test this by simulating the FPGA? If your'e really worried about interleaving, could you just wrap the FIFO.write method up in a subVI, that way you are 100% sure of the blocking?

Edit: Had a thought after I posted, how can you guarantee the order things are written to the FIFO? For example, what if the "slow" write actually executes first? Then your commands, while contiguous, will be "slower node" 1-12 then "faster node" 1-12. It seems to me you would have to serialize the two to ensure anything. 

Sorry if I'm not fully understanding your question.

[Intaris]

I actually don't mind which block gets sent first as long as the blocks in themselves are contiguous.  And yeah, the FIFO Write accepts arrays.  And yeah, you've understood my point well.

I'm also assuming that this will be the case but my experience shows that most assumptions (no matter how "intelligent" they might be) lead to unexpected (and very hard to track down) problems in the future......

I'd just love to hear an official NI stance on this.