Data Sharing In FPGA

[brijesh]

Dear Friends,

I am Using CRIO, I have a encoder. I am getting encoder input into the FPGA. That's Good.

What I have done is I places a timed loop and then wrote code for encoder. So I am getting all the parameter perfectly.

Like No Of pulse, Total Count, Forward Reverse, Reset On Z Pulse.

Now I want to logs Data at each encoder pulse and send to the RT though DMA. Very Good I can Do this. Now To Do this I have to put FPGA I/o Node Into this timed loop. But this gives compilation error. Good because Loops is not completing within time frame. So Compilation error.

So to over come I have to change timed loop to normal loop. I did I checked. But in this case I am not getting encoder input. So I have to stick to timed loop. Now what I have done is I placed another loop just above this and where I am taking data from the FPGA I/o Node and then though Local variable I am transferring data to timed loop(encoder loop)

Grt. Is this the Best way to do ?

Is there any other way to implement this. ?

Is there any interrupt based Method ?

Thanks you,

Brijesh Patel

India ...

[Nandagopal]

you can use Local FIFO to transfer the data from one loop to another in FPGA if you need higher data rate.

[brijesh]

Thanks For Responding,

Actually When I put FPGA I/O In time loop , My encoder parameter are not getting. So I have to find some other alternative.

May be local variable can be use but I am in search of some thing more precise and accurate method to do this.

Ya FIFO can be but in this case this is not applicable. Because I want to capture on Encoder Pulse and My FPGA I/O node is in Other Loop.

So when to fill Data In Fifo. If I fills continuously then it will get full. So I don't think is useful here.

I am in search of some interrupt based method.

Where at each encoder pulse a interrupt will be fired and that will get data for me and then I will ack that interrupt.

I don't know this is possible in FPGA. Ya there is interrupt based data methods are available but they are all based of target to host.

I don't find any Target to Target interrupt Fire Method.

Thanks You,

Brijesh Patel

[Nandagopal]

Interrupt in FPGA is possible. Do you know about occurance ???? 

Also the FIFO method helps, put the elements in the FIFO and take out the element parallelly in the other loop.

Thanks,

Nanda

[SimonD]

If your code is too long for a SCTL, you can also use pipelining with shift register.

[brijesh]

Ya That Sounds very good... Let me implement this let you know.

Thank you so much for responding, every one.

Brijesh Patel