Data acquisition using FPGA to read encoder through a bus using a pulse train that must pause with CLK+ set high

[jfjohnson3]

So I am trying to get data from an encoder using the SEA-9521 serial bus. I believe that I can get the loop correct on the timing  for the pulse train but one of the requirements to read data is that after a pulse train there needs to be a pause. While the pause is occouring the CLK+ must be set high for that time. I am not sure how to start the pause while the signal is at a high. I am using the Crio with FPGA on Labview 2018. If I could get any insight I would appreciate it.

[Terry_ALE]

Can you post code?

[Naim_LABVIEW_W]

Hello every one,

 Sorry for may message maybe it's not in the right discussion! but I need help if some one can figure out my problem.  I am new user of Labview, I use to use matlab and dSpace insteed.

I've got labviw 2012 ,I've also installed NIRIO120 for fpga drivers but I am still not able to see my chassis on my labview project (picture).

Could any one please help to resolve the problem and tell if I need to install something else ?

I am not connecting the labview to a real  RIO, I am just doing simulation on my computer.

Many thanks.

Regards,