12-02-2013 02:01 AM
Hello.
I'm trying to use multiple FPGA VIs in a same project, same target.
But, currently the Labview force me to re-compile when I want to run different FPGA VI in same project.
Even after compiling two FPGAs, the Labview program attempts to re-compile when I trying to run differnt FPGA VI.
So I refered http://zone.ni.com/reference/en-XX/help/371599G-01/lvfpgahelp/compiling_fpga_vis_howto/ to download compiled FPGA bit file to the target to transit to another FPGA VI.
However, still the Labview program trying to re-compile the FPGA VI when I click RUN on the VI after downloading compiled VI to the flash of the target.
How can I solve this problem?
P.S.:
I checked off the option of the build specification that the FPGA VI does not automatically run when it is loaded to target and the target switch is on.
12-02-2013 03:57 AM
Are you sharing VIs between the two top-level VIs?
If they have any conditional disable structures with different settings then the sub-VIs will be marked as changed when opening the top-level VI for your second target.
Do you need to run the code in interactive mode or can you simply compile a bitfile and use that instead. That was the compilation requirement disappears.
I agree though that LVs rush to mark VIs as changed is a problem for interactive FPGA mode.
Shane.