Embedding Xilinx System Generator in Labview FPGA

[irad]

Hi, 

There is an old paper titled "Integrating a Model from Xilinx SystemGenerator for DSP into LabVIEW FPGA". It says that Xilinx System Generator should be configured to produce an .ngc file. In Vivado System Generator this option is no longer available. How can it be done with the latest tools? Is there an updated version of the paper?

Kind regards, 

Ivan  

 

[ybalam]

It doesn't look like there's an updated version of the paper as far as I can tell, so I'm unsure if there's a way to do it with more current tools. Have you looked at the white paper for Importing External IP into LabVIEW FPGA?

[irad]

I have read that white paper but I still don't see how to solve the problem. I can get Xilinx System Generator to generate an HDL netlist, which outputs HDL source code files plus constraints files. However, from the Labview help file "Integrating Third-Party IP (FPGA Module)", it doesn't look like the IP integration node can take constraints files.  

[ybalam]

I have to admit, I'm not very familiar with Vivado/Xilinx--so forgive me if this still isn't quite what you're looking for, but I found an article that goes through file types of what both a CLIP node and an IP Integration Node can accept. It looks like, from Vivado, a CLIP node can take a constraint file in the form of a .xdc. Past that it looks like it can take a few different top level files and netlists. 

[BauerPower]

Hey Ivan, there are two ways to integrate HDL into LabVIEW FPGA: IP Integration Node (IPIN)  and Component Level IP (CLIP). For your use-case, you'll want to take the CLIP approach and use the CLIP wizard to add your VHDL and constraints to the LV Project under the FPGA target. Check out the following resources for more info!

http://zone.ni.com/reference/en-XX/help/371599G-01/lvfpgaconcepts/fpga_clip_tutor_intro/

http://www.ni.com/tutorial/7444/en/

[jion11]

Hi,I recently encountered the same problem as you. Have you solved your problem? How did you do it?