Errors in cRIO Programs

[prashiit]

Hello...

        I started working on cRIO-9074 with simple program. I tried to send the image from Host VI to FPGA VI by first converting the image into 1D array. I connected this 1D array to host2target DMA FIFO write. In FPGA VI, I added some numeric to the output elements of Host2target DMA FIFO Read function. Next, I connected the resultant to Target2host DMA FIFO write function. In host VI, I am trying to display the output of Target2host DMA FIFO Read function.  I am getting some errors in both FPGA VI and Host VI. 

Please see this simple example and let me know how to  correct them.

Thanks

Prashanth

[WillD]

First, the Host1.vi should be under the "Chasis" not "My Computer"

Floating point is not supported on the FPGA your constant of 2 should be an integer data type

An array of 1023 elements is most likely too much for the FPGA.  For this simple test you should reduce the element count to 64 or so.  When you define the FIFO the number that is displayed is the number of elements in the FPGA fabric.  The size of this depends on your data rates, but I have been able to get by with out issue setting this to the smallest value, 64, to save FPGA space.

[prashiit]

Hello..

      I need to work on image processing applications. But, image may not be of small size. Suppose image size is 160*160. First i will convert this image into 1D array of 160*160 elements. Now, how can I process whole image with out taking more space on FPGA.  I think I need to do iterative process. For, each iteration, I should send some amount of data.

       Can u please do this simple example for processing whole image and send it to me.... 

Thanks

Prashanth 

[WillD]

Yes you will need to do an iterative process with those data sizes, so long as your image "processing" allows it.

What processing are you trying to do?

Why do you need to do it on the FPGA, a general purpose processor isn't fast enough?

[prashiit]

It is an academic project. The aim of this project is to help under graduate students know about different processors/hardware. 

I have one doubt.  Generally, FPGAs are used for prototyping. Before doing ASIC design, they will first check the application on FPGA. But, why labview needs FPGA.

There are two modes of operation 1.scan interface mode 2.fpga interface mode

scan interface mode is for high speed data aquisition using FPGA I/Os but why fpga interface mode........??

Please clarify

Thanks

Prashh 

[WillD]

Scan mode just provides access to the C-Series module I/O.

The FPGA interface mode is used of you want to program logic on to the FPGA as well.  Most programming will use FPGA mode.  Scan interface just doesn't have the bandwidth to do high performance data manipulations.