Exporting Clock signal myRIO FPGA

[USF_ENG]

Hello I am trying to generate a clock signal at 32 MHz to send to an external ADC. I came across this example:

https://forums.ni.com/t5/Example-Programs/Three-3-Examples-of-Exporting-a-Clock-Signal-on-an-FPGA-De...

It is straightforward using a Single-cycle timed Loop with derived clock from the on-board oscillator at 40MHz. When I place an I/O node inside (or outside) I have a few minor issues for some reason. 

1) When I right click and click add new FPGA I/O nothing happens. I believe it should show the I/O line that I choose (ex DIO0). I can right click and select a constant and set that to the specific line. 

2) The FPGA I/O node defaults to a read mode, and I am trying to write. When I right click the node, the option to switch to write mode shows up, but when I click on it nothing happens. 

The target is added, but I'm not sure what I am missing. I'm sure it's something simple, but I'm stumped. I have attached the project folder. The vi I have been testing is called FPGA_Clock Testing.

Thanks for any help.

[wiebe@CARYA]

What happens when you try the example code from your link to the tutorial?

[USF_ENG]

I should have posted the error message, but come to find out this morning when I went to adjust the node and change to write it worked just as expected. I am not sure what changed between now and yesterday, but thanks for the reply