FPGA: DSA module + 9469 could run DSA on crazy sampling rates

[JCC_(SK)]

LabVIEW FPGA 2012

Do not repeat my mistake!

I used NI 9469 to generate higher accuracy timebase clock for NI 9239 DSA modules. Because synchronization module could be switch to import clock from external timebase clock I wanted to check that connection between Synchronization Modules wasn't lost and I placed "Check Clock Status" inside DSA acquisition loop.

Everything work fine for DSA sampling rates 10 kS/s and lower. But all higher sampling rates like 50 kS/s are running approximately at 11.6 kS/s.

DSA module doesn't return "under sample" error.

In NI 9469 mode method "Check Clock Status" help file is not mentioned that you should not to place it to acquisition loop.

My explanation of this behavior is: in FPGA code timebase line (trigger3) from Synch module is shared between DSA module and "Check Clock Status" and as result synch clock for DSA are running slower and sampling rate is lower as well.

Here is code snapshot:

Happy FPGA wiring

 Peter

[shruti.v]

Hello Peter, this is great! Thanks for that. I am sure more people would be able to use this if you put it up as a community example. So here's the link for it https://decibel.ni.com/content/community/zone . Feel free to upload anymore example code you create that you think could benefit others.

Kind Regards, 

Shruti