Hello all,
I believe I have found a bug in the Block Memory implementation of FIFO's on the FPGA, that shows up in single cycle timed loops.
It seems that there is a delay of 3 clock ticks (in this case) between the time any data goes in to the empty FIFO (fifo write) and it re-emerges from the fifo (fifo read). The problem goes away if I use flip-flops for the FIFO. But for a large FIFO, this is not a real option. The problem also "goes away" in emulation mode.
I am attaching a screen shot of "fpga_fifo_bug.vi" to illustrate the issue. I am also attaching the vi itself.
I hope you users or NI can set me straight, if I'm doing something wrong, or if its really a bug, I hope that NI will fix it soon.
Sincerely,
Peter H.
