FPGA FIFO overflow/timeout error

[vawter]

The FPGA FIFO write overflows pretty quickly, but even when it isn't overflowed, the RT FIFO read is unable to read any data and receives error -50400

[ZYOng]

My recommendation:

cRIO-9053 supports DAQmx. See Converting an NI-DAQmx VI Into a cRIO-904x LabVIEW Project

If you want to use FPGA for a specific reason, I would recommend using NI CompactRIO Waveform Reference Library

If you insist on writing your own DMA FIFO code, read Best Practices for DMA Applications (FPGA Module) and always refer to shipping examples to get started.

[vawter]

Thank you for the suggestions, I'll give them a look.

I made another post before because the DAQmx route was not working for me.  The cRIO was connected in MAX and in the project explorer, but when I tried to add the data channel to my block diagram, there was nothing to browse, and only a message of "(target disconnected)".  Maybe you have suggestions for that?