FPGA Fixed-Point compare

[Fefo]

Hi,

I have a problem in the FPGA programming.

Within a timed loop I try to compare two fixed-point values using a not equal? block. The first value comes from a fixed-point control and the second comes from a shift register.

The problem is that even if the two values are perfectly identical the not equal? block return a value that change with the time.

This is the screenshots of the code:

False case:

 

True case:

after the first loop, if the value of the Phase control don't change, the result of the not equal? block must be false but it toggles continously from true to false.

What is the cause of this behavior?

Can Anyone help me?

[Dagaror]

Buonasera,

Puoi mettere indicatori e vedere in ogni caso che valore indica?

Ciao