FPGA I/O Write Status - Sample Gated?

[10Things_Rob]

LabVIEW 2019.

I'm attempting to synchronize AI (9223) and AO (9262) on an FPGA using the User-Controlled I/O Sampling palette, and I'm getting my I/O Write Status Method reporting a "Sample Gated".

I go to the help and it says: "Sample Gated returns TRUE when the Generate I/O Sample Pulse Method function generates a sample pulse that is gated." (Thanks for the helpful tip!)

So my first set of questions are:

• What does Gated mean?
• Is this bad? (I assume so based on the 9262 Example that ships with LabVIEW)
• Did my point not output?
• If this IS actually an error condition, the example program does not actually treat it as such (by quitting the loop). Why not? Is that because the Error cluster will be set TRUE? (I haven't checked that part before... waiting on the compile to see that) Is that just poor coding in an Example program?

My second set of questions revolves around trying to understand causes and avoid this condition. According to the help, a sample pulse can be gated for the following reasons:

• The Generate I/O Sample Pulse Method function tries to execute more quickly than the maximum specified rate of the I/O item.
  • Question: how can I tell if this is the case? I am currently trying to run at 10kHz (I am eventually targeting 100kHz) and this is a 1MS card so I doubt that's the case
• Arbitration for the resource is occurring.
  • Question: how can I tell if this is the case? What causes this to happen? How can I avoid this if it IS the case? Seems unlikely if what I'm doing is very similar to the example
• The target is conducting an operation such that it cannot issue a clock pulse.
  • Question: how can I tell if this is the case? How can I avoid it if it IS the case?

My third set of questions involves how this actually works...

• Seems like each of these cards is using an internal buffer to store the the values associated with the AI/AO operations. In the 9262 example, the software makes sure that 2 elements have been written into the buffer before starting the write operation. How big is this buffer?
• Is there a way/need to monitor that buffer?

My fourth set of questions revolves around NI documentation:

•  Is there a white paper that actually explains this stuff that someone knows of? (I have serached but not found)
• Is there a way to provide feedback to NI about the Help section that is effective in producing change?
  
  

My fifth set of questions revolves around your experience:

• Have you done this kind of thing before?
• Have you seen an example that you can share with me?

Thanks in advance for your insights!

[Adam_Dewhirst]

These are all good questions. I attached a couple of presentations that explain the internal workings of the User Controlled I/O Sampling nodes and how they communicate with the modules.

These help show how to run at full speed, and explain what causes Sample Gated, Timeout, and other errors to occur.

Thanks,

-Adam

[LotsaMotsa]

Based on the 9262 timing waveforms, it looks like the sample rate is 1MS/s divided by the number of channels being written.  So if you are writing to two channels, the max sample rate is 500 kS/s per channel, correct?

How is the LV FPGA to 9262 module DB15 configured?  Is it a parallel bus able to carry parallel samples for all 6 channels or does one sample tie up the entire bus for ~1 us?

If it is 1 MS/s per channel, how do you interleave the separate writes?  Are there separate write node signal lines - one for each of the Write I/O nodes?  I guess I still have no idea how the interface bus works between the FPGA and 9262 module.

[Adam_Dewhirst]

The 9262 can update all the channels in parallel at 1 MS/s.

To achieve this rate in LV FPGA:

• Use the user-controlled I/O sampling API
• Grow the I/O Write Node to include all the channels you wish to update within the same node

When the I/O Write Node runs, it will transfer data for all channels to the module in parallel allowing you to update all channels at 1 MS/s.

[LotsaMotsa]

OK thank you.