I am trying to integrate a VHDL code which uses two Xilinx IPs DDS compiler and Adder/Subtracter.
In the FPGA IP Integration Node Properties dialogue box, the top level .vhd file and the IP core component .vhd files were loaded. Here is the error when I click on 'Generate' in page three. -
Generating simulation model for this IP...
Vivado Simulator 2017.2
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ERROR: [VRFC 10-149] 'dds_compiler_v6_0_16' is not compiled in library dds_compiler_v6_0_16 [C:\NIFPGA\iptemp\ipinF0828607E83C4C0CAF350A24308980DB\Vivado\sin_cos1.vhd:57]
INFO: [VRFC 10-307] analyzing entity sin_cos1
ERROR: [VRFC 10-1504] unit sin_cos1 ignored due to previous errors [C:\NIFPGA\iptemp\ipinF0828607E83C4C0CAF350A24308980DB\Vivado\sin_cos1.vhd:59]
INFO: [VRFC 10-240] VHDL file C:/NIFPGA/iptemp/ipinF0828607E83C4C0CAF350A24308980DB/Vivado/sin_cos1.vhd ignored due to errors
Generated IP unsuccessfully. Your source file(s) can't work for the FPGA famili(es) you select. Fix the above error(s) or warning(s) and generate the IP again, or go back to previous page to reselect FPGA Family Support.
Am I missing adding necessary files in page 1? Tried after selecting different FPGA families.