01-09-2010 01:35 PM
I am using a 9215 with a CRIO 9012. I have the iteration of the Single Point Timed Loop setup such that 1024 samples are taken in 1 second.
I have the AI channels fed into a DC-RMS FPGA calulation vi(s). I DO NOT HAVE THE RESET WIRED on the DC-RMS vi.
Do I have to set the reset true at the begining of every new data set? I ask this because the vi is NOT returning valid data. The vi is recieving data as it is toggling the output good flag to T
and there by setting the IRQ interrupt notifiying the CRIO host that it has a valid data set. Plus I have another indicator setup to pass teh point by point data for debugging purposes.
If I do not need to set the reset to TRUE does anyone know why the DC - RMS FPGA vi would not provide data?
Thanks
Tim C.
01-11-2010 04:19 PM