FPGA OVERMAPPED - What are my options?

[OSU_Spiegs]

I am getting an error when compiling my program for my CompactRIO/9102. My program is basically a big state machine that is controlling an Electron Beam deposition system.

How do I reduce:
1. Number of 4 input LUTs
2. Number of occupied Slices
3. Total Number 4 input LUTs

Is my overmapping an issue of too many variables or too many loops/sequences or both? Another issue is that it takes 6 hours to compile only to tell me after 6 hrs that I am overmapped. Is there a quicker way to find this out?

Thanks for your help,

Matt


Here's the error I get:

Design Summary:
Number of errors: 1
Number of warnings: 0
Logic Utilization:
Number of Slice Flip Flops: 7,876 out of 10,240 76%
Number of 4 input LUTs: 11,028 out of 10,240 107% (OVERMAPPED)
Logic Distribution:
Number of occupied Slices: 6,599 out of 5,120 128% (OVERMAPPED)
Number of Slices containing only related logic: 4,564 out of 6,599 69%
Number of Slices containing unrelated logic: 2,035 out of 6,599 30%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs: 12,627 out of 10,240 123% (OVERMAPPED)
Number used as logic: 11,028
Number used as a route-thru: 1,599

Number of bonded IOBs: 106 out of 324 32%
IOB Flip Flops: 8
Number of GCLKs: 1 out of 16 6%

Total equivalent gate count for design: 146,442
Additional JTAG gate count for IOBs: 5,088
Peak Memory Usage: 191 MB

[Arun_V]

Hello,

To define a Logic Slice, let me define a logic cell first. Logic cell consists of a lookup table, a flip flop, and connection to adjacent cells. Logic slice consists of 2 logic cells.

LUT is nothing but a Lookup table.

Overmapping error occurs when the VI needs more space than there is available on the FPGA. So there is no real way of telling whether the space has run out before compiling the code.

Bottomline, the code needs to be optimized for space. The code can be optimized by

1. Having only required controls and indicators in front panel. As all these are synthesized as registers.
2. Trying to avoid arrays
3. Using FPGA user memory instead of flip flops whenever possible (eg. when creating FIFO)
4. Single Cycle Timed Loop (SCTL). Code inside SCTL is automatically optimized for space.
5. Using shared resources.

Hope this helps.

Regards,

Arun V
National Instruments