FPGA Quadrature Generation for VeriStand

[joedowdle]

Hey all,

I have created this snippet of code to see what you might think of it.  I am unable to test it for the next week as the hardware is temporarily unavailable to me. I am pretty new to FPGA and very new to VeriStand, but I think this should work to create a Quadrature output.  I want to keep making progress so I'm just asking for anyone's opinion/thoughts about whether or not it should work.

Measuring the timing is most of my concern.  And do I need to worry about overflow with the timers?  I'm not 100% sure how these timers work. Do they just count indefinitely upwards?  And if that's the case, what is the best way to handle an overflow in this situation?

Thanks in advance.

[BillTür]

Hello,

I'm not sure if that is very useful in your case but have you considered using the Square Wave Generator function?

Also I'm not sure do you want the signal to have a certain period/frequency? Do you have while loop around the code? Is it maybe worth using a SCTL so you have a defined frequency?

The signal will be a PWM signal?

I think you should maybe take a look at the Square Wave Generator..

[joedowdle]

NOTE:  Before responding to the previous post... I noticed that I divided the period by 2 instead of 4.  Dividing by 2 would have given me a 180 degree phase difference rather than the 90 degrees that quadrature uses so I have changed that in my code to divide by 4 (it is NOT reflected in the snippet with the original post).

I have looked at the square wave generator but my primary reason for not using that is a lack of knowledge about how to implement the variables in the .fpgaconfig file.  I know how to use the PWM categories when setting up the .fpgaconfig file for use in VeriStand so I thought that if I make a quadrature by using two identical PWM's offset by 90 degrees that it would work just fine.  This would also allow the user to change the period and the duty cycle in the VeriStand system definition file of the quadrature (which has been requested by some of my team).

The reason there isn't a while loop around it is because it's a subVI in a SCTL that is in the main VI.  The SCTL includes a cluster of two channel constants, a U64 bit array with A and B hi/lo values in it, and a boolean for CW/CCW rotation.  The SCTL runs at the default clock speed (40 MHz).

I'm brand new in VeriStand so I don't know if this will work at all and as mentioned before I haven't been able to test anything yet on hardware so I am just trying to develop as much as I can without that.  If it would help I could post the main VI that I have set up for my FPGA.

Thanks for the input, I appreciate it and look forward to more.

[BillTür]

To be fair, I am not really familiar with VeriStand.

But from what I can see in the code this looks good. Have you tried running the VI on development computer? You will probably have to replace the digital outputs with something for visualisation.

The timers should be just fine. They overflow when the data width overflows but you won't have very long periods anyway.

[joedowdle]

I appreciate the input.  I am going to have to modify it though as there isn't an easy a way to control the period from VeriStand without having to restart your test.  I am going to have to take a slightly different route for this that I'm not sure of yet.  Also it's been requested to be able to adjust the phase +/- 45 degrees which shouldn't be too bad. 

Again, thanks for the input; it's appreciated.