FPGA Set Output Data and Set Output Enable

[wlmm10]

According to Using Set Output Data and Set Output Enable - NI R Series Multifunction RIO Device Drivers Help - Na..., the Set Output data controls the data output for a digital line while the Output enable controls the direction. Logic high is output, low is input.

I have a FPGA I/O (DIO) that is normally reads a data from an external tristate device through a connector pin as an input DIO. When the external input is tri-stated, I can use the Set output data and .Set output enable to feed this same DIO as an output. The enable is a logic high for only the time the data is active. This works.

With the same DIO, I can use a FPGA DIO node to continuously read the DIO within the FPGA. From this, I see both the external data and the data I generated internally using the Set output data/Set output enable path. This works.

However, I had expected to see my internally generated data on the connector pin for the FPGA, but I only see the externally generated data.

If the output enable allows the DIO to be an output, then why don't I see the my generated output on the external connector pin?

[wlmm10]

This issue is now resolved. The problem was that there was an external component that was driving the DIO low, creating contention. Once this contention was removed, the function works properly. I can now see my generated data, both internally and externally.

Using the Set Output data allows you to provide/change data to a given DIO, but it won't be seen until the enable is asserted. Using the Set Output enable, you control when the data is seen (both internally and externally at the same time). The same DIO can be read at any time.

The only requirement is if you are enabling an output on a DIO that is normally an input (input driven externally).For this case, you must ensure that the external network to the DIO is in high impedance when you enable your output for the DIO. So, yes, this is good for bi-direction communication.

If you use the DIO as an output only, the output enable could act as an independent pin gating function for the DIO (or a group of DIOs if you use the same enable for a port or a bus).

[spalinowy]

I have some questions about what you wrote.
1. how do you check that something is causing a conflict on the DIO?
2. how do you observe the current state on the line?
3. how do you make sure that the line is in a high impedance state?

[wlmm10]

1. how do you check that something is causing a conflict on the DIO?

A: Generally, one state on a DIO may dominate, so signaling on the DIO will be corrupted. LV FPGA cannot directly diagnose this, but faulty signaling can be seen by reading the DIO and could be diagnosed by adding additional logic to detect a deviation from the expected waveform.
2. how do you observe the current state on the line?

A: Externally, the DIO can be verified by a scope or by reading/using the DIO from whatever it is connected to (if the ability exists). Internally to the FPGA, you can always read the current state of the DIO.
3. how do you make sure that the line is in a high impedance state?

A: Internally, the OE for the DIO should be turned off. Externally to the DIO, you should be able to apply a high low pattern, such as a clock, without corruption. As in #1, you could send in a known pattern to verify good communication.

[spalinowy]

Thank you for your quick response.
I, too, by this time have already managed to fix the communication errors with Methods. In my case (for communication according to the I2C protocol) the NACK was generated wrong. So I had 50-70% wrong data.

I, on the other hand, used a logic state analyzer to observe the states. Excellent and helpful device, and costs only $10.