FPGA Simulation

[johnoc]

Hello, 

I am tryng to run an FPGA VI in simulation mode using the Desktop Exeecution node. The input to the VI is a Target-scope FIFO. Is there anyone that has any insight on how I can feed data into the FIFO to run simulation. Is it even possible?

[nathand]

Create a new VI that calls the one you want to run in simulation, and also put a loop in it that feeds data into the FIFO.

[johnoc]

Thank You! 

That seems to have worked for a target-scoped FIFO.

Now from the same VI I am outputting data to the host through a Target to Host DMA. Is there a way to access the DMA. I have tried providing a reference to the DMA in the same VI from which I call the Desktop Execution Node. I get an error code (-63195) anytime I try and use an Invoke Method on the DMA.

[nathand]

I haven't used the Desktop Execution Node, but it appears that you need to do the DMA transfer in parallel rather than sequentially. As you have your code configured in the screenshot, the FPGA code stops executing before you read from the DMA FIFO, resulting in the error. From the end of http://www.ni.com/white-paper/51859/en/ "FPGA applications that use DMA to transfer data to or from a host, and applications with large, complex host VIs require a different approach to the FPGA Desktop Execution Node. In these situations, you can use the FPGA Desktop Execution Node in parallel with the existing host VI."

Also, there is no need for the sequence structure in your code.

[johnoc]

I was mistaken the Target-scoped FIFO is not working correctly in simulation mode. I can write to it on the first iteration through the Desk Execution Node but since I am debugging an FPGA VI with an SCTL, where the FIFO read is located, it skips over the FIFO write in subsequent iterations. 

There is very little information on debugging more complex FPGA scenarios provided by NI. I just had an NI class on embedded systems aka Labview RT/FPGA and asked the instructor about debugging with FIFOs and DMA's and he pointed me to the same place you did. It's very frustrating when your using these products and information is so diffcult to find. I am not using LabVIEW 2015. The example you pointed me to requires 2015. Unfortunately I am in the middle of a project using 2014 and I am not upgrading in the middle of the project. Besides if the example provides as much help as other samples I have looked at it is a waste of time. The supporting documentation for many examples provided by NI is not the most helpful.

[nathand]

My experience simulating FPGA VIs is limited to earlier versions of LabVIEW, before the Desktop Execution Node was introduced. That said, I do now have LabVIEW 2014 with the FPGA toolkit available, so I'll see if I can help.

How are you writing to the target-scoped FIFO within your top-level FPGA VI? If you're reading from it within a single-cycle timed loop, then of course you'll also need to write to it at the same rate, otherwise there won't be data available. Is that what you're seeing now?

Can you share any of your code?