FPGA - Synchronize AI sampling with PWM generation

[riplakish]

Hello All,

I am currently working with a cRIO-9022 with 9113 chassis to control an inverter driven motor.  In my main FPGA VI I am sampling a current measurement via my 9215 AI module in a while loop and generating the center-aligned PWM signals for the inverter in a SCTL and outputting them using my 9401 DIO module.

The problem I'm having is that I'd like to ensure that my current sampling is not coinciding with any switching events in the PWM by synchronizing my sampling with the middle of the off time of my PWMs.  I've looked around for a way to trigger my sampling from a parallel loop and found the User-Controlled I/O Sampling pallette, which seems to have the functionality that I'm looking for.  However, my 9215 AI module does not appear to support those methods.

My question is this, before I go shelling out for a significantly more expensive AI module which does support those methods, is there any way to programmatically achieve this functionality with the hardware setup that I currently have?  It seems strange to me that this would be a special feature when it is something that is so easy to implement with any embedded controller with a PWM module.  Thanks for your help.

Regards

Joe

[thoult]

This isn't massively different from making your own sample and hold system.

The way I tend to implement it is a loop generating my digital output pulse, running nice and quickly with some sort of iteration decimator so I can control the period of the signal. When the output switches high, I generate an occurrence. In a parallel while loop, I have a wait on occurence function in a sequence structure frame. This frame blocks until the occurrence is generated, at which point it progresses to the next frame. At this point I usually have a delay to allow for sample and hold settling, then in the next frame the AI node.

Hope this makes sense. If not, I can try and knock something together when I get back to the office on Monday.

[riplakish]

Hi thoult,

Sorry for the lag, got side-tracked on another project after Thanksgiving.  I didn't have much familiarity with occurences before your reply, so I read up on them and looked at some examples.  Below is a stripped down version of my FPGA code with the occurrence functionality added.

The while loop on top generates the duty cycle of one of the two switching legs of an h-bridge inverter (called dA) operated under a unipolar switching scheme based on the ratio of the desired Vout to the DC bus voltage, here called Vdc.  Note that in my actual program Vout is a time-varying sinusoidal signal.  This loop also includes the wait on occurence function to control the sampling time of the ADC which samples the current measurement of the inverter load (Mod3/AI0), which is then written to an RT FIFO.

The SCTL below takes dA, calculates dB from it and with these two duty cycles calculates the rising and falling edges of the two symmetric PWM signals A and B based upon a counter which resets each switching cycle.  These PWMs and their complements are connected to digital outputs (Mod2/DIO0-3).  The set occurence function is used to trigger current sampling twice per switching period, once when the counter resets and again when the counter reaches its midpoint.  These two times correspond to the middle of the on-times and off-times respectively of the two PWM signals.  This ensures that sampling does not occur during a switching event (thereby avoiding sampling switching noise) and ensures a fixed sample rate Fs which is two times the switching frequency fsw.

The results when I run this code are overall positive.  I get the expected loop rate of Fs=2*fsw in my data acquisition loop, which tells me that the set/wait functions are working appropriately.  I also avoid the switching spikes which I was seeing during asynchronous sampling, but only to a point.  If my desired Vout is too large I start to pick up switching noise spikes on my current signal again.  My theory for this is that as Vout increases, so does dA, while dB decreases proportionally.  This means that my switching events are getting closer and closer to my two sampling times.  I believe that there is a small amount of delay between my set and wait on occurence functions which is causing my sampling to coincide with switching events at higher voltage outputs.

I'm open to any other explanations, however.  And of course with my limited experience with occurence functions, I'm very open to the possibility of improper execution of this functionality.  As always I am very grateful for the assistance.