LabVIEW

cancel
Showing results for 
Search instead for 
Did you mean: 

FPGA Timekeeper and PPS

Solved!
Go to solution

I use the FPGA TimeKeeper to synchronize my FlexRIO-7966 FPGAs to my PXIe controller's system clock.  This has been working well and give me roughly 5us of error.

 

Can a PPS input (From an external reference) be used to further increase the accuracy of the FPGA TimeKeeper?  If so, are there any alrogithms (FPGA VIs) already developed to do this?

 

Thanks,

 

XL600

0 Kudos
Message 1 of 4
(3,900 Views)
Solution
Accepted by xl600

If you download the FPGA Timekeeper 1.1b0.zip from the below link it will download the FPGA Timekeeper.lvlib, documentation, examples, and Timekeeper. In the example folder there is an example that shows how to synchronize to PPS.

 

https://forums.ni.com/t5/Example-Code/FPGA-Timekeeper-to-Timestamp-in-LabVIEW/ta-p/3538223

0 Kudos
Message 2 of 4
(3,838 Views)

I never noticed that example before.  Thanks!

 

I guess my next question would have to be:

 

The absolute time offset (ns) input.  How should that be populated initially?  My PPS signal is coming from an external system and I will be putting that through a PFI then routing it to a PXI_TRIG line.  I want the FPGA to be sync'd to the external host wall clock time.

 

My thinking is this:

 

If I read the time from the external host, obviously that time will be that host's time.  By the time I get it (Via Ethernet):

 

  • Iif the fractional seconds are <= 500ms, truncate it
  • Convert to ns
  • Update the absolute time offset
  • Start the timekeeper

 

The example VI would add 1s on the next PPS signal thus causing the timekeeper update to be the 'correct' time.  That would be the initialization sequence.

 

Sound about right?

 

Thanks,

 

XL600

0 Kudos
Message 3 of 4
(3,834 Views)

Sounds about right to me.

0 Kudos
Message 4 of 4
(3,801 Views)