FPGA VIs Launch Parallel Loops

[cbutcher]

Some potentially related thoughts:

• You could try global variables 😮
• It's possible to group controls/indicators on the FPGA FP so that when you want to use them on RT, they're neatly arranged (Group FPGA Controls With Dot Naming)
• I will note that the above sometimes seems to bug a bit (misgrouping, no runtime problems but weird at edit) if you use a bit file for linking rather than a build spec or VI. Probably version dependent, don't know...
• Clusters use more FPGA resources than their component parts, if the content is larger than 32 bits (Unable To Build FPGA VI After Grouping Controls in Arrays)

You might manage to bitpack values that you want to send to your FPGA such that they can be used more freely (via e.g. DMA FIFO) but that will depend on the use case and requirements.

[Intaris]

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@cbutcher wrote:

Some potentially related thoughts:

• You could try global variables 😮

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Not wanting to start a war, but VI-instantiated registers are better than Globals. You get a wire to see where the connections are.

Globals across clock domains are actually implementes as "Handshake" items internally. You'll get both latency and throughput issues. Not recommended. FIFO or BRAM are better (assuming you use synchronisation for BRAM).

[cbutcher]

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@Intaris wrote:

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@cbutcher wrote:

Some potentially related thoughts:

• You could try global variables 😮

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Not wanting to start a war, but VI-instantiated registers are better than Globals. You get a wire to see where the connections are.

Globals across clock domains are actually implementes as "Handshake" items internally. You'll get both latency and throughput issues. Not recommended. FIFO or BRAM are better (assuming you use synchronisation for BRAM).

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Seems like a good thing to be aware of if using multiple clock domains (I am not, but the OP mentioned they will/might use two after a couple of posts).