FPGA and real time halt at startup

[AlaaShaw]

I have project using FPGA as interface for collecting data from serial interface and DIO then passing this data to host for using this data in my program I have two FIFO read and write and I using both, my problem that when I start my program RT program from PC its running but halting (no data reach from FPGA, or when data reach the action from host to FPGA not done) in other way the program not working, I have to run it several times to work correctly.

Also when I deploy the RT into the target for starting the program (run at startup) the program to start in the target need to reset the target more than once to startup.

I guess that problem may come from several sources for example:-

1- timing between the FPGA and Host

2- Buffer FIFO (overflow, underflow, size,......)

3- Flushing or reset the serial interface

could u plz, from your experience advice me to know why this problem come, and how to trace it, also how to solve it.

alaa

[Shane-C]

Hello,

Have you been able to run any RT/FPGA code on this system before?  Are you using scan engine, or writting your own FPGA code?  You should be able to check and see if your FIFO is overflowing.  You can check how many elements remain in the FIFO, vs FIFO size, and you will know if it is overflowing.  Perhaps you could post some screen shots of your code to help give a better idea of what you are trying to do.

Regards,

Shane C

[AlaaShaw]

My project work with FPGA, also the program running with the error explained, many times before, i monitor error code in the fpga vi code (65572, and 65573).

[Shane-C]

Hello,

Can you post pictures of your code, or the code itself?  Also a screen shot of the error message?  The error messages you referenced deal with a break in serial communication.  Do you have serial communication in your program?

Regards,

Shane C

[AlaaShaw]

thank u for your interest, but i am so sorry i am hurry to do my project by solving this problem, i attach my FPGA vi to take a look, i have the RS232 c series serial 9870 and i used just two port one for read and other for write with baud rate 115200 bps.

[Shane-C]

Without seeing your code and hardware setup it is difficult to tell where this error is coming from, however if you take a look at the following link, you will be able to see the explanation for the error messages.

http://zone.ni.com/reference/en-XX/help/370984R-01/lvaddon11/987x_errors/

It sounds like your FPGA code is either not receiving any serial data, or data that is not formatted correctly.  You may want to check into that.

Shane C

[Domodo]

Good morning to everyone. Has anyone managed to solve this problem?

[raphschru]

Hi Domodo,

This thread is 10 years old, so you may better start a new topic. Your problem is probably different too. Give your software/hardware configuration and explain what you are trying to do. And please post your RT and FPGA codes (actual VI files, not images) saved for version LV2021 maximum.