FPGA compiling- Timing violation Error

[sam1371]

Hello all,

I am having a timing violation error while compiling my code to FPGA. I read the NI suggestions for solving this problem but it seems that none of the works for me. For example I can't use single-Cycle Timed Loop (SCTL) instead of the while loops because SCLT does not support the things inside my loops. I do not know what to do. Could you please take a look at the code and give me suggestions?

 (using NI SBRIO-9632 400 MHZ)

Best,

Samira

[WillD]

Using multiples of the same I/O node leads to timing issues on the FPGA, because of the arbitration resources required.

I would make a seperate loop to read/write global variables to 1 I/O node and replace the I/O nodes your provided code with reads/writes to the global variables.

The attached VI can use some clean up, but this minor change should get you running.