FPGA: first compile fails

[dan_u]

We have 2 machines with LV2012 SP1 including LV FPGA and the Xilinx Tools 13.4.

It is reproducible that the first compilation after starting the compile server (local) fails with an internal LV FPGA error. Just starting the compilation again (without even re-generating the intermediate files) works fine. Any clues?

We're compiling a FPGA code with a socketed CLIP on a 7965R target if that makes a difference.

On a side note: I'm happy sometimes some compile steps require a negative amount of time else the compilation would take even longer  I get this (cosmetic only) error from time to time.

[Nick-C]

dan_u,

Can you post a screenshot of the error? It sounds like generating intermediate files is succesful on the first attempt, so I am assuming the compile worker is actually being invoked. Can you post the a copy of your xilinx log for the compilation?

Before starting a the "first" compilation the next time, can you manually start the compile worker and see if the compilation proceeds as expected. You can manually run the compile worker from the Start Menu >> All Programs >> National Instruments >> FPGA Compile Tools >> FPGA Compile Worker

[dan_u]

Here's the screenshot from the compile error. Appears just after the state goes to "Estimating Resources using PlanAhead".

The error also occurs when I start the Compile Server manually before starting the compilation.

I attached the compile log (the 3 files are all I get in addition to the source vhdl files).

[Mellobuck]

Hello,

I have seen dan_u 's same screen in compiling FPGA for a single board RIO, (LV 2012 SP1), with the slight difference that if you wait the error disappears and the standard compiling updates continue to a successful bitfile. Dan_u, have you given it a minute or two before hitting [CLOSE]? Just making sure whether it is the same issue.

-Mello

[Nick-C]

dan_u,

When you click the "Details..." button, what information is there?

[dan_u]

---

@Mellobuck wrote:

Hello,

I have seen dan_u 's same screen in compiling FPGA for a single board RIO, (LV 2012 SP1), with the slight difference that if you wait the error disappears and the standard compiling updates continue to a successful bitfile. Dan_u, have you given it a minute or two before hitting [CLOSE]? Just making sure whether it is the same issue.

-Mello

---

I don't think it's still doing anything at that stage, and I'm quite sure I didn't always close the window when that happened (but of course restart the compilation). Anyway, even closing the window usually shouldn't do anything as it does not shut down the compiler.
I will check if it continues after a while just to be sure.

[dan_u]

Details... gives me this:

By searching for the error code I actually found an old thread about a similar error (same error code but different error text and different behavior of subsequent compilations) in LV2011: http://forums.ni.com/t5/Real-Time-Measurement-and/LabVIEW-FPGA-compiling-error-61330/m-p/1829675

And I can confirm that waiting doesn't change anything. The compile worker doesn't seem to still be doing anything at that stage.

[Naity]

Hi Dan,

What you see looks like a Bug that was supposed to be fixed in LabVIEW 2012 (CAR #354983). 

Is the issue only  happening with one project or with all of your projects? And do you know if it concerns only one workstation or if it can be reproduced elsewhere?

In the second case, could it be possible to get the project. I am curious to see if this still happens with LabVIEW 2013.

Best regards

[dan_u]

Hi Florian,

As mentioned in my first post we have 2 machines here and it happens on both of them.

Also, we have multiple project files and it happens with all of them.

I can't send or post a project, though. We're using a custom socketed CLIP and I can't share it. I will see if I can reproduce the issue without CLIP or with a NI CLIP.

[Naity]

Hi Dan, 

Sorry, I skipped the information in your first post.

It would be helpful if you could try with an NI CLIP or without a CLIP. 

If this seem to be related with your CLIP only and reproducible, there might be only 2 soltuions: ignoring it or checking if there it can be handed over with a company based NDA (the best would be to clear this up with your local Branch)

Best Regards