FPGA library linkage breaks

[LabLoko]

Hi All,

I've developed some FPGA code on the 32 bit myrio FPGA platform 2019 and all works well for a while but occasionally the linkage of the FPGA subVI's (on the Labview FPGA side) fails and the VI breaks. I then need to re-complile the directory including the FPGA code to re-establish those links. Following that i need to re-compile.

Any ideas why this might be the case ? My only concern is that I also run a Labview 2020 64 bit for another application running at the same time. Could i be that the two are cross-confusing linkages to the proper FPGA sub-VI's ?

Cheers

Jamie

[Terry_ALE]

There shouldn't be cross linking, check dependencies in case there are https://zone.ni.com/reference/en-XX/help/371361R-01/lvconcepts/avoiding_incorrect_dependencies/

One thing that may reduce the save requests is to separate source and compiled code https://zone.ni.com/reference/en-XX/help/371361R-01/lvhowto/separate_compiled_code/

Regarding the recompile requests, I'd point to the bitfile and not the VI in Open FPGA VI.  This way even slight loading changes (i.e. not logic) does not ask for a recompile.

[LabLoko]

Hi Terry,

Thanks for your prompt reply. I'll take your links into account and point to the bitfile instead of the VI in future. I should point out though that the subVI's missing were the FPGA VI's related to timing etc that come with the FPGA distribution (loop timer etc). I dont know why their links just break on occassion.

Cheers

Jamie